`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/03/08 23:00:38
// Design Name: 
// Module Name: code_key
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module code_key(
input wire clk,
input wire clr,
input [7:0] code,
input [1:0]din,
output pass,
output fail
    );
    parameter s0 = 1000,s1 = 1100, s2 = 1110,s3 = 1111,E1 = 0111,E2 = 0011,E3 = 0001,E4 = 0000;
    reg [3:0] nowstate,nextstate;
    always@(posedge clk)
    begin
        if (clr == 0)
        nowstate <= s0 ;
        else
        nowstate <= nextstate; 
    end

endmodule
